The present invention relates to a semiconductor memory device constituted by bipolar transistors, and more particularly to a read/write control circuit controlling a data-read operation and a data-write operation.
In a semiconductor bipolar memory device, each of bipolar transistor memory cells includes first and second bipolar transistors of a multi-emitter type having first and second emitters, first and second load resistors, and first and second clamping diodes. The first emitters of the first and second transistors are connected in common to a data holding current source. The base and collector of the first transistor are connected to the collector and base of the second transistor, respectively. The first load resistor and clamping diode are connected in parallel between the collector of the first transistor and a word line, and the second load resistor and clamping diode are connected in parallel between the collector of the second transistor and the word line.
Assuming that the first and second transistors are made conductive and non-conductive, respectively, the data holding current flows through the first transistor. Accordingly, the collector voltage of the first transistor, i.e., the base voltage of the second transistor, is lower than the base-emitter threshold voltage of the second transistor to maintain the second transistor in a non-conductive state. Since no current flows through the second transistor, the collector voltage of the second transistor (i.e., the base voltage of the first transistor) is larger than the base-emitter threshold voltage of the first transistor. The first transistor is thereby held in a conductive state. This condition means that the data "1" is stored in the memory cell. On the contrary, the data "0" is stored in the cell when the first and second transistors are in the nonconductive and conductive states, respectively. The first and second clamping diodes are provided for suppressing the lowering of the collector potentials of the first and second transistors upon the data-read and data-write operations to attain a high speed operation, and therefore Schottky diode having a forward voltage lower than that of a p-n junction diode is employed for the first and second clamping diodes. When the clamping diode is turned on, the collector potential of the transistor is clamped to a potential that is obtained by subtracting the forward voltage of the clamping diode from the selective level of the word line. Upon the data holding condition, the level of the word line takes an unselective level and the current from the data holding current source is considerably small. Therefore, both of the first and second clamping diodes are turned off.
In order to read out the data stored in the memory cell, there is provided a data detection circuit which includes third and fourth transistors and first and second reading-out current sources. The emitter of the third transistor and the second emitter of the first transistor are connected in common to the first reading-out current source, and the emitter of the fourth transistor is connected to the second reading-out current source along with the second emitter of the second transistor. The difference in voltages between the collectors of the third and fourth transistors is amplified and then used as a read-out data output.
In the data-read operation, the read/write control circuit supplied a reading-out voltage to the bases of the third and fourth transistors. If the data "1" is stored in the selected memory cell, the first and second transistors are in the conductive state and in the non-conductive state, respectively. The increased current by the selective level on the word line thereby flows through the first transistor to enhance the voltage drop across the first load resistor. The first clamping diode is thus turned on. As a result, the potential at the collector of the first transistor (i.e., at the base of the second transistor) is clamped to a level that is obtained by subtracting the ON voltage of the first clamping diode from the selective level on the word line. On the other hand, the second load resistor is supplied with the base current of the first transistor, and hence its voltage drop is negligible. The base of the first transistor takes the selective level on the word line. Accordingly, the difference between the base potentials of the first and second transistors is substantially equal to the ON voltage (or forward voltage) of the clamping diode. In order to obtain the difference in voltage between the collectors of the third and second transistors, the reading-out voltage should take an intermediate level between the base potentials of the first and second transistors.
In a read/write control circuit according to the prior art, two resistors are provided in series between power supply terminals, and the reading-out voltage is derived from the connection point of these resistors. The potential of the reading-out voltage is thereby determined by the resistance ratio of the resistors and the power supply voltage applied between the power supply terminals. Since the resistance ratio of two or more resistors formed in an integrated circuit device can be designed with a considerable accuracy, the deviation in the potential of the reading-out voltage is very small. On the other hand, Schottky diodes are employed for the clamping diodes, and the forward voltage (ON voltage) of a Schottky diode is changed in a relatively wide range in accordance with the variation in the manufacturing process conditions. In other words, the difference between the base potentials of the first and second transistors is varied relatively. For this reason, the reading-out voltage often takes a potential that is out of the level range from the base potential of the first transistor to that of the second transistor.
In order to overcome such a shortcoming, a read/write control circuit has been proposed, in which the ON voltage (forward voltage) of Schottky diode is divided by at least two resistors and the divided voltage is used as the read-out voltage. More specifically, the same level as the selective level of the word line is applied to the anode of the Schottky diode whose cathode is connected to a constant current source. Two resistors are connected in series between the anode and cathode of the Schottky diode, and the potential at the connection point of the resistors is derived as the reading-out voltage. The current of the constant current source is designed to be equal to that of the reading-out current source, and the sum of the resistance values of the two resistors is choosen to take the same value of the road resistor in the memory cell. The ON voltage of the Schottky diode is thereby made substantially equal to that of the clamping diode in the memory cell. In addition, the change in ON voltage of the respective diodes caused by the variation in manufacturing process is made similar to each other. As a result, the reading-out voltage produced by this circuit arrangement takes an intermediate potential between the base potentials of the first and second transistors, irrespective of the variation in manufacturing process.
However, the charging and discharging the input capacitances of the third and fourth transistors and the stray capacitances of interconnection wiring layers are carried out through the two resistors connected in series between the anode and cathode of the Schottky diode. The load resistor in the memory cell has a resistance value of several tens kilo-ohms due to a low power consumption and a high speed operation, and therefore the resistance values of the two resistors for producing the reading-out voltage should be designed to several tens kilo-ohms. For this reason, the time constant for charging and discharging the input capacitances and stray capacitances becomes large, resulting in that the speed of the data-read operation is made slow.